Design Automation Conference expected to set records

نویسندگان

  • Larry Dunn
  • Larry O'Neill
چکیده

The 22nd Design Automation Conference, to be held June 23-26 at Caesars Palace in Las Vegas is likely to set several records. According to Larry Dunn, publicity chairman, more than 284 papers were submitted from authors in 18 countries. The program committee has accepted 126 of these papers for presentation in technical sessions and tutorials. About 80 companies will be showing their products, many of them new, at the exhibition that complements the technical sessions. Almost all the well-known names in the design automation field will be represented, as well as some intriguing newcomers. Program chairman Larry O'Neill said, "The primary goal of the DAC is to provide a high-quality technical program that meets the needs of the engineering community. To remain current, an engineer must be aware of both technical innovation and commercially available systems to perform the operations. Thus, exhibits have become an integral part of the DAC, but they are controlled to be in balance with, and augment, the technical program." O'Neill pointed to session 27 in the technical program (on Tuesday afternoon) as an example of the unity of the program and exhibits. In that session, representatives of various design-automation equipment manufacturers will present short papers on technical aspects of their systems. O'Neill expects Monday afternoon's panel session "Computer-Aided Tools Integration and Related Standards Development in a Multivendor Universe" will be particularly useful and interesting. This panel gets people who are involved in a variety of design-automation programs "all in one place at one time. " The panelists will discuss their experiences in integrating design-automation tools from various manufacturers into working systems. Fifteen papers have been nominated for Best Paper at this year's conference. The winners will be announced at a press conference on Sunday, between 1 and 3 p.m., in the exhibit area. The papers were nominated in three categories: Layout, Verification and Silicon Compilation; Design Simulation and Test; and Systems, Languages and Software. The nominated papers, by category, are:

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

This paper presents the results of a formal logic verification system implemented as part of MIS, the multi-level logic synthesis system developed at U. C. Berkeley. Combinational logic verification involves checking two networks for functional equivalence. Techniques that flatten networks or use cube enumeration and simulation cannot be used with functions that have very large cube covers. Bin...

متن کامل

MetaCore: An Application Specific DSP Development System - Design Automation Conference, 1998. Proceedings

This paper describes the MetaCore system which is an ASIP(App1ication-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration an...

متن کامل

PALACE: a layout generator for SCVS logic blocks - Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permuting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking tinung requir...

متن کامل

ERIF Final Report Analysis and Optimization of Sequential Circuits under Process Variations

The proposed project for the statistical static timing analysis (SSTA) problem of latch-based sequential circuits under process variations was completed. The research result was presented at 15th IEEE/ACM Asia and South Pacific Design Automation Conference, Taipei, Taiwan, Jan. 18– 21, 2010, which is one of the top peer-reviewed international conferences in the field of electronic design automa...

متن کامل

High-level synthesis techniques for functional test pattern execution1

Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in designs, and therefore the intermediate variables in functional specifications. We propose a new divide-and-conquer approach for maximizing the simultaneous controllability of an arbitrary set of the user selected variables...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1985